1. Field of the Invention
The present invention relates to a communication apparatus and a method therefor, and particularly, relates to a communication apparatus and a method for attaching a checksum for error detection to data to be sent to a network such as the Internet or a local area network (LAN).
2. Description of the Related Art
In recent years, such a communication apparatus has been required to perform checksum attachment processing at high speed in order to deliver high quality images over the Internet and through moving image transfer.
For example, Japanese Patent Application Publication No. 2006-303765 discloses a communication apparatus that performs checksum attachment processing in accordance with Transmission Control Protocol (TCP)/Internet Protocol (IP). FIG. 10 shows an example of a configuration of this communication apparatus.
The communication apparatus 1x shown in FIG. 10 includes a central processing unit (CPU) 10, a main memory 20, an interface circuit 110 that functions as an interface between the CPU 10 and the main memory 20, a TCP/IP transmission processing circuit 120, a TCP/IP reception processing circuit 130, a media access control (MAC) processing circuit 50 connected to the circuits 120 and 130, and a physical layer processing circuit 60 (hereinafter, PHY processing circuit) connected between this MAC processing circuit 50 and an Ethernet (registered trademark) cable 2. Here, the CPU 10, the main memory 20, and the interface circuit 110 are mutually connected through a bus 70. Moreover, a hard disk drive (HDD) 80, an input unit 90, and a display unit 100 are connected to the bus 70. A web browser program, a mail client program, and the like used by the CPU 10 are recorded in the HDD 80. The input unit 90 receives an input from a user (not shown). The display unit 100 displays results on processing performed by the CPU 10 to the user.
In other words, in the communication apparatus 1x, as shown by a dotted line in FIG. 10, the MAC processing circuit 50 and the PHY processing circuit 60 act as a network interface layer Lt1 in a TCP/IP hierarchical model. The interface circuit 110, the TCP/IP transmission processing circuit 120, and the TCP/IP reception processing circuit 130 act as an Internet layer and transport layer Lt2. Further, the CPU 10, the main memory 20, and the HDD 80, the input unit 90, and the display unit 100 act as an application layer Lt3.
The TCP/IP transmission processing circuit 120 includes a direct memory access (DMA) processor 121, a check sum controller 122, a buffer memory 123, and a check sum calculator 124. Further, the checksum controller 122 has an IP checksum register 125 therein.
In data sending operation, first, the CPU10 executes the above-mentioned web browser program, mail client program, or the like to generate an Ethernet frame FRe shown in FIG. 11 in the main memory 20.
Here, the Ethernet frame FRe is a frame in which a MAC header HD3 and a frame check sequence (FCS) are attached to a TCP/IP stream data SD including an IP header HD1, a TCP header HD2, and a payload PL. Here, the FCS is generated and attached by the MAC processing circuit 50, as will be described later.
The IP header HD1 alone is a target for check sum calculation, and includes a version, a header length, a type, a packet length (TCP/IP stream data length), a packet identification number, a flag, a fragmentation offset, a TTL (Time To Live), an upper layer protocol number, an IP checksum field Fc1, a sending source IP address, a destination IP address, and an option field. Out of these, the IP checksum field Fc1 is a field for storing a calculated checksum CSi for the IP header HD1 (hereinafter, referred to as an IP checksum).
Further, the TCP header HD2 as well as the payload PL and a TCP pseudo header HD4 shown in FIG. 11 are targets for checksum calculation. The TCP header HD2 includes a sending source port number, a destination port number, a sequence number, an Ack number, an offset, a Reserved area, various flags such as URG, ACK, PSH, RST, SYN, and FIN, a Window size, a TCP checksum field Fc2, an Urgent pointer, and an option field. Out of these, the TCP checksum field Fc2 is a field for storing a calculated checksum CSt for the TCP header HD2, the payload PL, and the TCP pseudo header (hereinafter, referred to as a TCP checksum).
When the CPU 10 generates the above-mentioned Ethernet frame FRe (except for the FCS) in the main memory 20, the DMA processor 121 in the TCP/IP transmission processing circuit 120 performs DMA transfer of the frame FRe from the main memory 20 to the checksum controller 122 through the interface circuit 110 (Step S101), as shown in FIG. 12. More specifically, the DMA processor 121 transfers the MAC header HD3, the IP header HD1, the TCP header HD2, the payload PL, and the TCP pseudo header HD4 in this order to the checksum controller 122.
First, the checksum controller 122 receives the MAC header HD3 from the DMA processor 121. At this time, the checksum controller 122 writes the received MAC header HD3 into the buffer memory 123 (Step S102).
Next, the checksum controller 122 receives the IP header HD1 from the DMA processor 121. At this time, the checksum controller 122 writes the received IP header HD1 into the buffer memory 123 (Step S103), and also transfers the IP header HD1 to the checksum calculator 124 (Step S104). The checksum calculator 124 calculates the IP checksum CSi (Step S105), and returns the IP checksum CSi to the checksum controller 122 (Step S106). Then, the checksum controller 122 stores the IP checksum CSi in the IP checksum register 125 (Step S107).
Subsequently, the checksum controller 122 receives the TCP header HD2 and the payload PL from the DMA processor 121. At this time, the checksum controller 122 writes the received TCP header HD2 and payload PL into the buffer memory 123 (Step S108), and also transfers the TCP header HD2 and payload PL to the checksum calculator 124 (Step S109).
Thereafter, the checksum controller 122 receives the TCP pseudo header HD4 from the DMA processor 121. At this time, the checksum controller 122 transfers the received TCP pseudo header HD4 to the checksum calculator 124 (Step S110). Since the TCP pseudo header HD4 is used only for calculation of the TCP checksum CSt (that is, the TCP pseudo header HD4 is not sent to the network), the checksum controller 122 does not write the TCP pseudo header HD4 into the buffer memory 123, unlike the above-mentioned steps S103 and S108. As a result, the MAC header HD3, the IP header HD1, the TCP header HD2, and the payload PL are stored in the buffer memory 123.
Then, the checksum calculator 124 calculates the TCP checksum CSt (Step S111), and returns the TCP checksum Cst to the checksum controller 122 (Step S112).
Subsequently, the checksum controller 122 reads the MAC header HD3, the IP header HD1, the TCP header HD2, and the payload PL, which are stored in the buffer memory 123 (Step S113), and starts to sequentially transfer the read MAC header HD3, IP header HD1, TCP header HD2 and payload PL to the lower layer (MAC processing circuit 50 shown in FIG. 10).
More specifically, firstly, the checksum controller 122 transfers the MAC header HD3 read from the buffer memory 123 to the MAC processing circuit 50 (Step S114).
Secondly, the checksum controller 122 inserts (writes) the IP checksum CSi stored in the IP checksum register 125 into the IP checksum field Fc1 of the IP header HD1 read from the buffer memory 123, and then transfers the IP header HD1 to the MAC processing circuit 50 (Step S115).
Thirdly, the checksum controller 122 inserts the TCP checksum CSt received at the above-mentioned step S112 into the TCP checksum field Fc2 of the TCP header HD2 read from the buffer memory 123, and then transfers the TCP header HD2 to the MAC processing circuit 50 (Step S116).
Lastly, the checksum controller 122 transfers the payload PL read from the buffer memory 123 to the MAC processing circuit 50 (Step S117).
The MAC processing circuit 50 attaches the FCS to an end of a frame consisting of the MAC header HD3, the IP header HD1, the TCP header HD2, and the payload PL received from the checksum controller 122, and then transfers the frame to the PHY processing circuit 60. Thereby, the Ethernet frame FRe is sent to the Ethernet cable 2 (namely, a network) through the PHY processing circuit 60.
However, Japanese Patent Application Publication No. 2006-303765 has a problem that the TCP/IP transmission processing circuit needs to have a buffer memory capacity large enough to store TCP/IP stream data, and thus needs to be made large in circuit scale.
Japanese Patent Application Publication No. 2001-268159 discloses a communication apparatus in which a buffer memory for storing checksum target data received from an upper layer, and a buffer memory for storing data after checksum writing are provided separately. With this configuration, the communication apparatus executes checksum calculation processing and data send processing in parallel. However, this communication apparatus needs a larger buffer memory capacity for the checksum attachment processing, than that of Japanese Patent Application Publication No. 2006-303765, thereby making the circuit scale much larger.